A conventional implementation of a synchronizer 10 involves the utilization of a flip-flop 12 and a flip-flop 14 in a cascaded configuration, as shown in FIG. 1. The flip-flops 12 and 14 attempt to reduce the probability of metastable behavior of the synchronized signal. For the cases when the frequency of the input clock signal is higher than that of the output clock signal, there is a risk that short input pulses may be missed by the flip-flop 12, thus being filtered by the synchronization logic.
Some of the undesirable behavior of the synchronizer 10 of FIG. 1 can be avoided by implementing an SR flip-flop in the input clock domain, along with additional feedback logic. FIG. 2 illustrates such an architecture 20 including a one-shot state machine 22, a double synchronizer 24, a double synchronizer 26 and a SR flip-flop 28. The SR flip-flop 28 and the double synchronizer 24 are clocked by a signal CLOCK_IN. The double synchronizer 26 is clocked by a signal CLOCK_OUT. The double synchronizers 24 and 26 can each contain the circuitry of the synchronizer 10 of FIG. 1 and are implemented in both the feed-forward and feedback paths.
The circuit 20 has a high latency and recovery time due to the implementation of the two double synchronizers 24 and 26. In addition, the circuit 20 requires a relatively large number of storage elements, which increases the implementation area and overall power consumed.